1. Field of the Invention
This invention relates to a manufacturing method of a semiconductor device, specifically to a manufacturing method of a semiconductor device having an LDD (Lightly Doped Drain) structure and silicide layers formed on a silicon substrate and a gate electrode.
2. Description of the Related Art
As a manufacturing process of a semiconductor device moves to a finer design rules, there arises a problem that characteristics of a MOS transistor decline due to a short channel effect. A technology called LDD has been developed and used as a countermeasure against the problem. Another problem is resistance increase of a gate electrode and source and drain regions due to reduced dimensions of the gate electrode and the source and drain regions. A technology called salicide is used as a countermeasure against the problem. Silicide layers are formed in a self-aligned manner around surfaces of the gate electrode and the source and drain regions by a reaction between transition metal and silicon in the salicide technology. Many of semiconductor devices in recent years have been manufactured by a combination of these two technologies.
A manufacturing process of the semiconductor device using the combination of the LDD structure and the salicide technology will be briefly described hereafter, referring to FIGS. 9–14.
A gate insulation film 12 is formed on a silicon substrate 11, as shown in FIG. 9. A silicon oxide film is generally used as the gate insulation film 12. A film of a material to make a -gate electrode 13 is formed on the gate insulation film 12. The gate electrode 13 is formed through subsequent photolithography and etching. After that, low impurity concentration regions 14 are formed by injecting a low dose of impurities into a surface of the silicon substrate 11, using the gate electrode 13 as a mask.
An insulation film is formed over the silicon substrate 11, as shown in FIG. 10. This insulation film is hereafter referred to as a spacer insulation film 15.
A spacer 16 is formed on each sidewall of the gate electrode 13 by dry-etching the spacer insulation film 15 and the gate insulation film 12 anisotropically, as shown in FIG. 11.
A buffer film 17 made of an insulation film is formed over the silicon substrate 11, as shown in FIG. 12. A high dose of impurities is injected into the silicon substrate to form high impurity concentration regions 18. After forming the high impurity concentration regions 18, the buffer film 17 is removed by dry-etching.
A transition metal film 19 is formed over the entire surface of the silicon substrate 11, as shown in FIG. 13. Heating the silicon substrate 11 causes a reaction between the transition metal film 19 and silicon, which is a material of the silicon substrate 11 and the gate electrode 13, to form silicide made from the transition metal and silicon. After removing a portion of the transition metal film 19 which has not reacted with silicon, the silicon substrate 11 is heated again to form silicide layers 20 on the surface of the silicon substrate 11 and on a surface of the gate electrode 13, as shown in FIG. 14.
Although not shown in the figure, the rest of the manufacturing process to complete the semiconductor device including forming an interlayer insulation film, opening contact holes in the high impurity concentration regions and forming metal wirings is well known in the art.
There arise following problems when a semiconductor device is manufactured by the above-mentioned technologies to form the LDD structure and the silicide layer.
First, in etching the insulation film to make the spacer 16 and the buffer film 17, usually a gas including carbon such as CF4 or CHF3 is used. This results in residual carbon left on the surface of the silicon substrate 11 and the surface of the gate electrode 13, more specifically in regions about 4 nm deep from the surface. The residual carbon is referred to as a carbon contamination hereafter.
Second, over-etching which takes place in forming the spacer 16 and in removing the buffer film 17 inevitably removes a surface portion of the silicon substrate, as shown in elliptical regions a in FIG. 11 and in elliptical regions b in FIG. 12. As a result, thicknesses of the low impurity concentration regions 14 and the silicide layers 20 to be formed later are reduced.
One time of the over-etching removes about 7–15 nm of the surface portion of the silicon substrate 11, thus two times of the over-etching removes about 14–30 nm of the surface portion of the silicon substrate 11.
Third, the reaction between the transition metal and silicon is hampered in regions where the carbon contamination has taken place, thus the silicide layer may not be formed in elliptical regions c in FIG. 14, leaving non-reacted portions of the transition metal there. Countermeasures against this problem such as plasma treatment on the carbon-contaminated regions and etching to remove the carbon-contaminated regions are described in the aforementioned patents.
Up to 34 nm of the surface portion of the silicon substrate is removed by the over-etching and removing the carbon-contaminated regions as described above. Reducing the thickness by about 34 nm does not cause a major problem when an ordinary silicon substrate is used, since the whole substrate is made of thick silicon.
However, it causes a big problem with a wafer having a thin substrate 11 of crystalline silicon grown on an insulator 21 as in the case of SOI (Silicon On Insulator) which has been brought into use in recent years, as shown in FIG. 15. Since the silicon substrate 11 on the insulator 21 is as thin as about 50–100 nm, removing the surface portion of the silicon substrate 11 by about 34 nm means a substantial reduction in the thicknesses of the high and low impurity concentration regions and the silicide layers. This results in a decline in characteristics of a transistor in the semiconductor device. The transistor does not operate in some cases, because the high and low impurity concentration regions and the silicide layers are not thick enough for the transistor to operate.
There is another problem that resistances of the source and drain regions and the gate electrode vary with locations on the wafer, since an etch rate and a selection ratio of the dry-etching vary with the locations on the wafer.